ST STM32G4 Series Reference Manual page 667

RM0440
Bits 22:18 SQ13[4:0]: 13th conversion in regular sequence
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
Bit 17 Reserved, must be kept at reset value.
Bits 16:12 SQ12[4:0]: 12th conversion in regular sequence
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
Bit 11 Reserved, must be kept at reset value.
Bits 10:6 SQ11[4:0]: 11th conversion in regular sequence
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
Bit 5 Reserved, must be kept at reset value.
Bits 4:0 SQ10[4:0]: 10th conversion in regular sequence
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
20.6.14 ADC regular sequence register 4 (ADC_SQR4)
Address offset: 0x3C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:11 Reserved, must be kept at reset value.
These bits are written by software with the channel number (0..18) assigned as the 13th in
the regular conversion sequence.
no regular conversion is ongoing).
These bits are written by software with the channel number (0..18) assigned as the 12th in
the regular conversion sequence.
no regular conversion is ongoing).
These bits are written by software with the channel number (0..18) assigned as the 11th in
the regular conversion sequence.
no regular conversion is ongoing).
These bits are written by software with the channel number (0..18) assigned as the 10th in
the regular conversion sequence.
no regular conversion is ongoing).
28 27 26 25
Res. Res. Res.
12 11 10 9
Res.
rw rw
24 23 22
Res. Res. Res.
8 7 6
SQ16[4:0]
rw rw rw
RM0440 Rev 1
Analog-to-digital converters (ADC)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. SQ15[4:0]
rw rw rw
17 16
Res. Res.
1 0
rw rw
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