Figure 614. Pdm Typical Connection And Timing - ST STM32G4 Series Reference Manual

Serial audio interface (SAI)
Like interrupt generation, the SAI can use the DMA if DMAEN bit in the SAI_xCR1 register is
set. The FREQ bit assertion mechanism is the same as the interruption generation
mechanism described above for FREQIE.
Each FIFO is an 8-word FIFO. Each read or write operation from/to the FIFO targets one
word FIFO location whatever the access size. Each FIFO word contains one audio slot.
FIFO pointers are incremented by one word after each access to the SAI_xDR register.
Data should be right aligned when it is written in the SAI_xDR.
Data received will be right aligned in the SAI_xDR.
The FIFO pointers can be reinitialized when the SAI is disabled by setting bit FFLUSH in the
SAI_xCR2 register. If FFLUSH is set when the SAI is enabled the data present in the FIFO
will be lost automatically.
39.3.10 PDM Interface
The PDM (Pulse Density Modulation) interface is provided in order to support digital
microphones. Up to 4 digital microphone pairs can be connected in parallel.
shows a typical connection of a digital microphone pair via a PDM interface. Both
microphones share the same bitstream clock and data line. Thanks to a configuration pin
(LR), a microphone can provide valid data on SAI_CK[m] rising edge while the other
provides valid data on SAI_CK[m] falling edge (m being the number of clock lines).
1. n refers to the number of data lines and p to the number of microphone pairs.
The PDM function is intended to be used in conjunction with SAI_A subblock configured in
TDM master mode. It cannot be used with SAI_B subblock. The PDM interface uses the
timing signals provided by the TDM interface of SAI_A and adapts them to generate a
bitstream clock (SAI_CK[m]).
1766/2083

Figure 614. PDM typical connection and timing

SAI
TDM link
M
TDM link
SAI_A
MpL MpR MpL MpR MpL MpR MpL MpR MpL
SAI_Dn
SAI_CKm
SAI_Dn
SAI_CKm
RM0440 Rev 1
RM0440
Figure 614
Vcc
LR
MpL
GND
LR
MpR
MSv35467V6