ST STM32G4 Series Reference Manual page 682

Analog-to-digital converters (ADC)
Table 166. ADC register map and reset values for each ADC (offset=0x000
Offset Register
0x44-
Reserved
0x48
ADC_JSQR
0x4C
Reset value 0
0x50-
Reserved
0x5C
ADC_OFR1
0x60
Reset value 0
ADC_OFR2
0x64
Reset value 0
ADC_OFR3
0x68
Reset value 0
ADC_OFR4
0x6C
Reset value 0
0x70-
Reserved
0x7C
ADC_JDR1
0x80
Reset value
ADC_JDR2
0x84
Reset value
ADC_JDR3
0x88
Reset value
ADC_JDR4
0x8C
Reset value
0x8C-
Reserved
0x9C
ADC_AWD2CR
0xA0
Reset value
ADC_AWD3CR
0xA4
Reset value
0xA8-
Reserved
0xAC
682/3748
for master ADC, 0x100 for slave ADC) (continued)
JSQ4[4:0] JSQ3[4:0]
0 0 0 0 0 0 0
OFFSET1_
CH[4:0]
0 0 0 0 0 0 0
OFFSET2_
CH[4:0]
0 0 0 0 0 0 0
OFFSET3_
CH[4:0]
0 0 0 0 0 0 0
OFFSET4_
CH[4:0]
0 0 0 0 0 0 0
Res.
JSQ2[4:0]
0 0 0 0 0 0 0
Res.
Res.
0 0
0 0
0 0
0 0
Res.
0 0 0 0 0
0 0 0 0 0
RM0440 Rev 1
JEXTSEL
JSQ1[4:0]
0 0 0 0 0 0 0 0 0
OFFSET1[11:0]
0 0 0 0 0 0 0
OFFSET2[11:0]
0 0 0 0 0 0 0
OFFSET3[11:0]
0 0 0 0 0 0 0
OFFSET4[11:0]
0 0 0 0 0 0 0
JDATA1[15:0]
0 0 0 0 0 0 0 0 0
JDATA2[15:0]
0 0 0 0 0 0 0 0 0
JDATA3[15:0]
0 0 0 0 0 0 0 0 0
JDATA4[15:0]
0 0 0 0 0 0 0 0 0
AWD2CH[18:0]
0 0 0 0 0 0 0 0 0
AWD3CH[18:0]
0 0 0 0 0 0 0 0 0
RM0440
JL[1:0]
[4:0]
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0