Table 251. Behavior Of Timer Outputs Versus Tim_Brk/Tim_Brk2 Inputs; Figure 315. Pwm Output State Following Tim_Brk And Tim_Brk2 Assertion (Ossi=1) - ST STM32G4 Series Reference Manual

Advanced-control timers (TIM1/TIM8/TIM20)
The tim_brk has a higher priority than tim_brk2 input, as described in
Note: tim_brk2 must only be used with OSSR = OSSI = 1.
tim_brk
Active
Inactive
Figure 315
signals on tim_brk and tim_brk2 inputs. In this case, both outputs have active high polarities
(CCxP = CCxNP = 0 in TIMx_CCER register).

Figure 315. PWM output state following tim_brk and tim_brk2 assertion (OSSI=1)

tim_brk2
tim_brk
tim_ocx
tim_ocxn
I/O state
1092/2083

Table 251. Behavior of timer outputs versus tim_brk/tim_brk2 inputs

Timer outputs
tim_brk2
– Inactive then
forced output
state (after a
deadtime)
X
– Outputs disabled
if OSSI = 0
(control taken
over by GPIO
logic)
Active
gives an example of tim_ocx and tim_ocxn output behavior in case of active
Deadtime
Active Inactive
tim_ocxn output
state
(low side switches)
ON after deadtime
insertion
Inactive
RM0440 Rev 1
Table 251.
Typical use case
tim_ocx output
(high side switches)
OFF
Deadtime
Idle
RM0440
OFF
OFF
MSv62338V1