Table 259. Timx Register Map And Reset Values - ST STM32G4 Series Reference Manual

RM0440
Bits 31:0 DMAB[31:0]: DMA register for burst accesses
27.6.31 TIMx register map
TIMx registers are mapped as 16-bit addressable registers as described in the table below:
Offset Register
TIMx_CR1
0x000
Reset value
TIMx_CR2
0x004
Reset value
TIMx_SMCR
0x008
Reset value
TIMx_DIER
0x00C
Reset value
TIMx_SR
0x010
Reset value
TIMx_EGR
0x014
Reset value
TIMx_CCMR1
Input Capture
mode
Reset value
0x018
TIMx_CCMR1
Output
Compare mode
Reset value
TIMx_CCMR2
Reset value
0x01C
TIMx_CCMR2
Reset value
A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA
transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).

Table 259. TIMx register map and reset values

MMS2[3:0]
0 0
0 0
0
0
0
0
Advanced-control timers (TIM1/TIM8/TIM20)
0 0 0 0 0 0 0
TS
[4:3]
0 0 0 0 0
0 0 0 0
0 0 0 0 0
IC2F[3:0]
0 0
0 0 0
0 0 0
IC4F[3:0]
0 0
RM0440 Rev 1
CKD CMS
[1:0] [1:0]
0 0 0 0 0 0
0 0 0 0 0 0 0 0
ETP
S ETF[3:0] TS[2:0]
[1:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0
IC2 CC2
PSC S IC1F[3:0]
[1:0] [1:0]
0 0 0 0 0 0 0 0
CC2
OC2M OC1M
S
[2:0]
[1:0]
0 0 0 0 0 0 0 0
CC4
OC4M OC3M
S
[2:0]
[1:0]
0 0 0 0 0 0 0 0
IC4 CC4
PSC S IC3F[3:0]
[1:0] [1:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0
MMS
[2:0]
0 0 0 0 0
SMS[2:0]
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
IC1 CC1
PSC S
[1:0] [1:0]
0 0 0 0 0 0
CC1
S
[2:0]
[1:0]
0 0 0 0 0 0
CC3
S
[2:0]
[1:0]
0 0 0 0 0 0
IC3 CC3
PSC S
[1:0] [1:0]
0 0 0 0 0 0
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