Figure 89. Enabling / Disabling The Adc - ST STM32G4 Series Reference Manual

Analog-to-digital converters (ADC)
ADEN
ADRDY
ADDIS
ADC
state
by S/W
20.4.10 Constraints when writing the ADC control bits
The software is allowed to write the RCC control bits to configure and enable the ADC clock
(refer to RCC Section), the control bits DIFSEL in the ADC_DIFSEL register and the control
bits ADCAL and ADEN in the ADC_CR register, only if the ADC is disabled (ADEN must be
equal to 0).
The software is then allowed to write the control bits ADSTART, JADSTART and ADDIS of
the ADC_CR register only if the ADC is enabled and there is no pending request to disable
the ADC (ADEN must be equal to 1 and ADDIS to 0).
For all the other control bits of the ADC_CFGR, ADC_SMPRx, ADC_TRy, ADC_SQRy,
ADC_JDRy, ADC_OFRy, ADC_OFCHRy and ADC_IER registers:
•
For control bits related to configuration of regular conversions, the software is allowed
to write them only if the ADC is enabled (ADEN=1) and if there is no regular conversion
ongoing (ADSTART must be equal to 0).
•
For control bits related to configuration of injected conversions, the software is allowed
to write them only if the ADC is enabled (ADEN=1) and if there is no injected
conversion ongoing (JADSTART must be equal to 0).
•
ADC_TRy registers can be modified when an analog-to-digital conversion is ongoing
(refer to
AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx,
The software is allowed to write the ADSTP or JADSTP control bits of the ADC_CR register
only if the ADC is enabled, possibly converting, and if there is no pending request to disable
the ADC (ADSTART or JADSTART must be equal to 1 and ADDIS to 0).
The software can write the register ADC_JSQR at any time, when the ADC is enabled
(ADEN=1). Refer to
additional details.
Note: There is no hardware protection to prevent these forbidden write accesses and ADC
behavior may become in an unknown state. To recover from this situation, the ADC must be
disabled (clear ADEN=0 as well as all the bits of ADC_CR register).
578/3748

Figure 89. Enabling / Disabling the ADC

t
STAB
OFF Startup RDY
by H/W
Section 20.4.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL,
Section 20.6.16: ADC injected sequence register (ADC_JSQR)
RM0440 Rev 1
Converting CH
RDY
AWDx)for details).
RM0440
REQ
OFF
-OF
MSv30264V2
for