General-purpose timers (TIM15/TIM16/TIM17)
Table 284
tim_brk inputs
TIM_BKIN
tim_brk_cmp1
tim_brk_cmp2
tim_brk_cmp3
tim_brk_cmp4
tim_brk_cmp5
tim_brk_cmp6
tim_brk_cmp7
tim_sys_brk
inputs
tim_sys_brk0
tim_sys_brk1
tim_sys_brk2
tim_sys_brk3
tim_sys_brk4
Table 286
Timer OCREF clear
tim_ocref_clr0
tim_ocref_clr1
tim_ocref_clr2
tim_ocref_clr3
tim_ocref_clr4
tim_ocref_clr5
tim_ocref_clr6
tim_ocref_clr7
1304/2083
and
Table 285
list the sources connected to the tim_brk input.
Table 284. Timer break interconnect
TIM15_BKIN pin
comp1_out
comp2_out
comp3_out
comp4_out
comp5_out
comp6_out
comp7_out
Table 285. System break interconnect
TIM15 / TIM16 / TIM17
®
Cortex
-M4 with FPU LOCKUP
Programmable Voltage Detector (PVD)
SRAM parity error
Flash ECC error
Clock Security System (CSS)
lists the internal sources connected to the tim_ocref_clr input multiplexer.
Table 286. Interconnect to the ocref_clr input multiplexer
signal
comp1_out
comp2_out
comp3_out
comp4_out
comp5_out
comp6_out
comp7_out
TIM15
TIM16_BKIN pin
comp1_out
comp2_out
comp3_out
comp4_out
comp5_out
comp6_out
comp7_out
Timer OCREF clear signals assignment
TIM15
comp1_out
comp2_out
comp3_out
comp4_out
comp5_out
comp6_out
comp7_out
RM0440 Rev 1
TIM16
TIM17_BKIN pin
Enable bit in SYSCFG_CFGR2
register
CLL
PVDL
SPL
ECCL
None (always enabled)
TIM16
Reserved
RM0440
TIM17
comp1_out
comp2_out
comp3_out
comp4_out
comp5_out
comp6_out
comp7_out
TIM17
comp1_out
comp2_out
comp3_out
comp4_out
comp5_out
comp6_out
comp7_out
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