Flash Pcrop1 Start Address Register (Flash_Pcrop1Sr) - ST STM32G4 Series Reference Manual

Embedded Flash memory (FLASH) for category 3 devices
3.7.9

Flash PCROP1 Start address register (FLASH_PCROP1SR)

Address offset: 0x24
Reset value: 0xFFFF XXXX. Register bits are loaded with values from Flash memory at
OBL.
Access: no wait state when no Flash memory operation is on going, word access.
31 30 29
Res. Res. Res. Res.
15 14 13
Res.
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Bit 16 IDWG_SW: Independent watchdog selection
0: Hardware independent watchdog
1: Software independent watchdog
Bit 15 Reserved, must be kept cleared
Bit 14 nRST_SHDW
0: Reset generated when entering the Shutdown mode
1: No reset generated when entering the Shutdown mode
Bit 13 nRST_STDBY
0: Reset generated when entering the Standby mode
1: No reset generate when entering the Standby mode
Bit 12 nRST_STOP
0: Reset generated when entering the Stop mode
1: No reset generated when entering the Stop mode
Bit 11 Reserved, must be kept cleared
Bits10:8 BOR_LEV: BOR reset Level
These bits contain the VDD supply level threshold that activates/releases the
reset.
000: BOR Level 0. Reset level threshold is around 1.7 V
001: BOR Level 1. Reset level threshold is around 2.0 V
010: BOR Level 2. Reset level threshold is around 2.2 V
011: BOR Level 3. Reset level threshold is around 2.5 V
100: BOR Level 4. Reset level threshold is around 2.8 V
Bits 7:0 RDP: Read protection level
0xAA: Level 0, read protection not active
0xCC: Level 2, chip read protection active
Others: Level 1, memories read protection active
Note: Take care about PCROP_RDP configuration in Level 1. Refer to
Level 1: Read protection
28 27 26 25
Res. Res. Res.
12 11 10 9
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for more details.
24 23 22
Res. Res. Res. Res.
8 7 6
PCROP1_STRT[14:0]
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RM0440 Rev 1
21 20 19 18
Res. Res. Res.
5 4 3 2
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RM0440
Section :
17 16
Res. Res.
1 0
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