Figure 556. Lpuart Block Diagram - ST STM32G4 Series Reference Manual

Low-power universal asynchronous receiver transmitter (LPUART)
37.3 LPUART functional description
37.3.1 LPUART block diagram
lpuart_wkup
lpuart_it
lpuart_tx_dma
lpuart_rx_dma
lpuart_pclk
lpuart_ker_ck
The simplified block diagram given in
domains:
•
The lpuart_pclk clock domain
The lpuart_pclk clock signal feeds the peripheral bus interface. It must be active when
accesses to the LPUART registers are required.
•
The lpuart_ker_ck kernel clock domain
The lpuart_ker_ck is the LPUART clock source. It is independent of the lpuart_pclk
and delivered by the RCC. So, the LPUART registers can be written/read even when
the lpuart_ker_ck is stopped.
When the dual clock domain feature is disabled, the lpuart_ker_ck is the same as the
lpuart_pclk clock.
There is no constraint between lpuart_pclk and lpuart_ker_ck: lpuart_ker_ck can be
faster or slower than lpuart_pclk, with no more limitation than the ability for the software to
manage the communication fast enough.
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Figure 556. LPUART block diagram

IRQ Interface
lpuart_pclk
clock domain
DMA Interface
COM Controller
LPUART_CR1
LPUART_ISR
LPUART_CR2
LPUART_CR3
LPUART_RQR
LPUART_ICR
LPUART_TDR
LPUART_RDR
LPUART_
RTOR
LPUART_
GTPR
LPUART_BRR
LPUART_
PRESC
Figure 556
RM0440 Rev 1
lpuart_ker_ck clock domain
Hardware
flow control
TX Shift Reg
...
RX Shift Reg
...
Baudrate
generator &
orversampling
lpuart_ker_ck_pres
shows two fully independent clock
RM0440
LPUART
CK
CTS/NSS
RTS/DE
TX
RX
MSv40858V3