Figure 280. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6; Figure 281. Counter Timing Diagram, Internal Clock Divided By 2 - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus

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Advanced-control timers (TIM1/TIM8/TIM20)

Figure 280. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6

Counter register

Counter underflow

Counter overflow

Update event (UEV)

Update interrupt flag

Here, center-aligned mode 1 is used (for more details refer to

Counter register

Counter underflow

Update event (UEV)

Update interrupt flag

Section 27.6: TIM1/TIM8/TIM20

RM0440 Rev 1

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