ST STM32G4 Series Reference Manual page 444

CORDIC co-processor (CORDIC)
16.4.3 CORDIC result register (CORDIC_RDATA)
Address offset: 0x8
Reset value: 0x0000 0000
31 30 29
15 14 13
Bits 31:0 RES: Function result
444/2083
28 27 26 25
12 11 10 9
If 32-bit format is selected (CORDIC_CSR.RESSIZE = 0) and two output values are
expected (CORDIC_CSR.NRES = 1), this register must be read twice when the RRDY flag
is set. The first read will fetch the primary result (RES1). The second read will fetch the
secondary result (RES2), and reset RRDY.
If 32-bit format is selected and only one output value is expected (NRES = 0), only one read
of this register is required to fetch the primary result (RES1) and reset the RRDY flag.
If 16-bit format is selected (CORDIC_CSR.RESSIZE = 1), this register contains the primary
result (RES1) in the lower half, RES[15:0], and the secondary result (RES2) in the upper
half, RES[31:16]. In this case, NRES must be set to 0, and only one read performed.
A read from this register resets the RRDY flag in the CORDIC_CSR register.
24 23 22
RES[31:16]
r
8 7 6
RES[15:0]
r
RM0440 Rev 1
21 20 19 18
5 4 3 2
RM0440
17 16
1 0