Table 365. Sai Interrupt Sources - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus
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Serial audio interface (SAI)
Follow the sequence below to configure the SAI interface in DMA mode:
1.
Configure SAI and FIFO threshold levels to specify when the DMA request will be
launched.
2.
Configure SAI DMA channel.
3.
Enable the DMA.
4.
Enable the SAI interface.
Note:
Before configuring the SAI block, the SAI DMA channel must be disabled.
39.4
SAI interrupts
The SAI supports 7 interrupt sources as shown in
Interrupt
Interrupt
source
group
FREQ
FREQ
OVRUDR
ERROR
AFSDET
ERROR
LFSDET
ERROR
CNRDY
ERROR
MUTEDET
MUTE
WCKCFG
ERROR
Follow the sequence below to enable an interrupt:
1.
Disable SAI interrupt.
2.
Configure SAI.
3.
Configure SAI interrupt source.
4.
Enable SAI.
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Table 365. SAI interrupt sources

Audio block mode
Master or slave
Receiver or transmitter
Master or slave
Receiver or transmitter
Slave
(not used in AC'97 mode
and SPDIF mode)
Slave
(not used in AC'97 mode
and SPDIF mode)
Slave
(only in AC'97 mode)
Master or slave
Receiver mode only
Master with NODIV = 0 in
SAI_xCR1 register
Table
Interrupt enable
FREQIE in SAI_xIM
register
OVRUDRIE in
SAI_xIM register
AFSDETIE in
SAI_xIM register
LFSDETIE in
SAI_xIM register
CNRDYIE in
SAI_xIM register
MUTEDETIE in
SAI_xIM register
WCKCFGIE in
SAI_xIM register
RM0440 Rev 1
365.
Interrupt clear
Depends on:
– FIFO threshold setting (FLVL bits in
SAI_xCR2)
– Communication direction (transmitter
or receiver)
For more details refer to
Section 39.3.9: Internal FIFOs
COVRUDR = 1 in SAI_xCLRFR register
CAFSDET = 1 in SAI_xCLRFR register
CLFSDET = 1 in SAI_xCLRFR register
CCNRDY = 1 in SAI_xCLRFR register
CMUTEDET = 1 in SAI_xCLRFR
register
CWCKCFG = 1 in SAI_xCLRFR register
RM0440

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