Figure 341. Directional Index Sensitivity; Figure 342. Counter Reset As Function Of Fidx Bit Setting - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus

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IDIR[1:0]=00

IDIR[1:0]=01

IDIR[1:0]=10

Special first index event management

The FIDX bit in the TIMx_ECR register allows the Index to be taken only once, as shown on

ignored. If needed, the circuitry can be re-armed by writing the FIDX bit to 0 and setting it

When FIDX = 1, the index can be issued twice (IDXF flag set) if the direction changes at

position 0 (index active).

Figure 341. Directional index sensitivity

below. Once the first index has arrived, any subsequent index will be

Advanced-control timers (TIM1/TIM8/TIM20)

RM0440 Rev 1

Down-counting

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