Figure 563. Transmission Using Dma - ST STM32G4 Series Reference Manual

RM0440
Idle preamble
TX line
TXE flag
DMA request
F1
USART_TDR
TC flag
DMA writes
USART_TDR
DMA TCIF flag
(transfer
complete)
Software
DMA writes
configures DMA
F1 into
to send 3 data
USART_TDR
blocks and
enables USART
Note: When FIFO management is enabled, the DMA request is triggered by Transmit FIFO not full
(i.e. TXFNF = 1).
Reception using DMA
DMA mode can be enabled for reception by setting the DMAR bit in LPUART_CR3 register.
Data are loaded from the LPUART_RDR register to a SRAM area configured using the DMA
peripheral (refer to the corresponding
whenever a data byte is received. To map a DMA channel for LPUART reception, use the
following procedure:
1. Write the LPUART_RDR register address in the DMA control register to configure it as
the source of the transfer. The data is moved from this address to the memory after
each RXNE (RXFNE in case FIFO mode is enabled) event.
2. Write the memory address in the DMA control register to configure it as the destination
of the transfer. The data is loaded from LPUART_RDR to this memory area after each
RXNE (RXFNE in case FIFO mode is enabled) event.
3. Configure the total number of bytes to be transferred to the DMA control register.
4. Configure the channel priority in the DMA control register
5. Configure interrupt generation after half/ full transfer as required by the application.
6. Activate the channel in the DMA control register.
When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector.
Low-power universal asynchronous receiver transmitter (LPUART)

Figure 563. Transmission using DMA

Frame 1
Set by hardware
cleared by DMA read
F2
Set by hardware
DMA writes DMA writes
F2 into F3 into
USART_TDR USART_TDR
RM0440 Rev 1
Frame 2
Set by hardware
cleared by DMA read
F3
Cleared
by
software
The DMA
transfer is
Software waits until TC=1
complete
(TCIF=1 in
DMA_ISR)
Direct memory access controller (DMA)
Frame 3
Set by hardware
Ignored by the DMA because
the transfer is complete
ai17192b
section)
Set by
hardware
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