ST STM32G4 Series Reference Manual page 344

Peripherals interconnect matrix
ADC trigger selection
EXTSEL[4:0] or
JEXTSEL[4:0]
20
21
22
23
24
25
26
27
28
29
30
31
Timers (TIMx, HRTIM) can be used to generate an ADC triggering event.
TIMx synchronization is described in:
ADC synchronization is described in:
trigger polarity (EXTSEL, EXTEN,JEXTSEL,
Triggering signals
The output (from timer) is on signal TIMx_TRGO, TIMx_TRGO2 or TIMx_CCx event.
The input (to ADC) is on signal EXT[15:0], JEXT[15:0].
The connection between timers and ADC is provided in:
• Table 152: ADC1/2 - External triggers for regular channels
•
Table 153: ADC1/2 - External trigger for injected channels
Active power mode
Run, Sleep, Low-power run, Low-power sleep.
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Table 54. Interconnect 19 (continued)
ADC1/2
Regular
tim20_cc3 hrtim_adc_trg4
hrtim_adc_trg1 hrtim_adc_trg5
hrtim_adc_trg3 hrtim_adc_trg6
hrtim_adc_trg5 hrtim_adc_trg7
hrtim_adc_trg6 hrtim_adc_trg8
hrtim_adc_trg7 hrtim_adc_trg9
hrtim_adc_trg8 hrtim_adc_trg10
hrtim_adc_trg9
hrtim_adc_trg10
lptim_out
tim7_trgo
-
RM0440 Rev 1
ADC triggers signals assignment
Injected
hrtim_adc_trg4
hrtim_adc_trg1
hrtim_adc_trg3
hrtim_adc_trg5
hrtim_adc_trg6
hrtim_adc_trg7
hrtim_adc_trg8
TIM16_CC1 hrtim_adc_trg9
- hrtim_adc_trg10
lptim_out
tim7_trgo
-
Section 27.3.31: ADC synchronization
Section 20.4.18: Conversion on external trigger and
JEXTEN).
ADC3/4/5
Regular Injected
hrtim_adc_trg4
hrtim_adc_trg5
hrtim_adc_trg6
hrtim_adc_trg7
hrtim_adc_trg8
hrtim_adc_trg9
hrtim_adc_trg10
hrtim_adc_trg1
hrtim_adc_trg3
lptim_out lptim_out
tim7_trgo tim7_trgo
-
(TIM1/TIM8).
RM0440
-