ST STM32G4 Series Reference Manual page 281

RM0440
Bit 1 TIM3SMEN: TIM3 timer clocks enable during Sleep and Stop modes
Bit 0 TIM2SMEN: TIM2 timer clocks enable during Sleep and Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.
6.4.24 APB1 peripheral clocks enable in Sleep and Stop modes register 2
(RCC_APB1SMENR2)
Address offset: 0x7C
Reset value: 0x0000 0103
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 UCPD1SMEN: UCPD1 clocks enable during Sleep and Stop modes
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 I2C4SMEN: I2C4 clocks enable during Sleep and Stop modes
Bit 0 LPUART1SMEN: Low power UART 1 clocks enable during Sleep and Stop modes
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.
2. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.
Set and cleared by software.
0: TIM3 clocks disabled by the clock gating
1: TIM3 clocks enabled by the clock gating
Set and cleared by software.
0: TIM2 clocks disabled by the clock gating
1: TIM2 clocks enabled by the clock gating
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
Set and cleared by software.
0: UCPD1 clocks disabled by the clock gating
1: UCPD1 clocks enabled by the clock gating
Set and cleared by software
0: I2C4 clocks disabled by the clock gating
1: I2C4 clock enabled by the clock gating
Set and cleared by software.
0: LPUART1 clocks disabled by the clock gating
1: LPUART1 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
24 23 22
Res. Res. Res. Res.
8 7 6
UCPD1
Res. Res. Res.
SMEN
rw
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(2)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
(1)
RM0440 Rev 1
Reset and clock control (RCC)
21 20 19 18
Res. Res. Res.
5 4 3 2
Res. Res. Res.
during Sleep and Stop modes
during Sleep and Stop modes
17 16
Res. Res.
1 0
LP
I2C4
UART1
SMEN
SMEN
rw rw
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