ST STM32G4 Series Reference Manual page 543

RM0440
When writing the control register (QUADSPI_CR) the user specifies the following settings:
•
The enable bit (EN) set to '1'
•
The DMA enable bit (DMAEN) for transferring data to/from RAM
•
Timeout counter enable bit (TCEN)
•
Sample shift setting (SSHIFT)
•
FIFO threshold level (FTRHES) to indicate when the FTF flag should be set
•
Interrupt enables
•
Automatic polling mode parameters: match mode and stop mode (valid when
FMODE = 11)
•
Clock prescaler
When writing the communication configuration register (QUADSPI_CCR) the user specifies
the following parameters:
•
The instruction byte through the INSTRUCTION bits
•
The way the instruction has to be sent through the IMODE bits (1/2/4 lines)
•
The way the address has to be sent through the ADMODE bits (None/1/2/4 lines)
•
The address size (8/16/24/32-bit) through the ADSIZE bits
•
The way the alternate bytes have to be sent through the ABMODE (None/1/2/4 lines)
•
The alternate bytes number (1/2/3/4) through the ABSIZE bits
•
The presence or not of dummy bytes through the DBMODE bit
•
The number of dummy bytes through the DCYC bits
•
The way the data have to be sent/received (None/1/2/4 lines) through the DMODE bits
If neither the address register (QUADSPI_AR) nor the data register (QUADSPI_DR) need to
be updated for a particular command, then the command sequence starts as soon as
QUADSPI_CCR is written. This is the case when both ADMODE and DMODE are 00, or if
just ADMODE = 00 when in indirect read mode (FMODE = 01).
When an address is required (ADMODE is not 00) and the data register does not need to be
written (when FMODE = 01 or DMODE = 00), the command sequence starts as soon as the
address is updated with a write to QUADSPI_AR.
In case of data transmission (FMODE = 00 and DMODE! = 00), the communication start is
triggered by a write in the FIFO through QUADSPI_DR.
Status flag polling mode
The status flag polling mode is enabled setting the FMODE field (QUADSPI_CCR[27:26]) to
10. In this mode, the programmed frame will be sent and the data retrieved periodically.
The maximum amount of data read in each frame is 4 bytes. If more data is requested in
QUADSPI_DLR, it will be ignored and only 4 bytes will be read.
The periodicity is specified in the QUADSPI_PISR register.
Once the status data has been retrieved, it can internally be processed i order to:
• set the status match flag and generate an interrupt if enabled
•
stop automatically the periodic retrieving of the status bytes
The received value can be masked with the value stored in the QUADSPI_PSMKR and
ORed or ANDed with the value stored in the QUADSPI_PSMAR.
RM0440 Rev 1
Quad-SPI interface (QUADSPI)
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