Table 247. System Break Interconnect; Table 248. Interconnect To The Ocref_Clr Input Multiplexer - ST STM32G4 Series Reference Manual

RM0440
tim_brk2 inputs
tim_brk2_cmp2
tim_brk2_cmp3
tim_brk2_cmp4
tim_brk2_cmp5
tim_brk2_cmp6
tim_brk2_cmp7
tim_sys_brk
inputs
tim_sys_brk0
tim_sys_brk1
tim_sys_brk2
tim_sys_brk3
tim_sys_brk4
Table 248
Timer OCREF clear
tim_ocref_clr0
tim_ocref_clr1
tim_ocref_clr2
tim_ocref_clr3
tim_ocref_clr4
tim_ocref_clr5
tim_ocref_clr6
tim_ocref_clr7
27.3.3 Time-base unit
The main block of the programmable advanced-control timer is a 16-bit counter with its
related auto-reload register. The counter can count up, down or both up and down. The
counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software, even when the counter is running.
Table 246. Timer break2 interconnect (continued)
TIM1
comp2_out
comp3_out
comp4_out
comp5_out
comp6_out
comp7_out

Table 247. System break interconnect

TIM1 / TIM8 / TIM20
®
Cortex -M4 with FPU LOCKUP
Programmable Voltage Detector (PVD)
SRAM parity error
Flash ECC error
Clock Security System (CSS)
lists the internal sources connected to the tim_ocref_clr input multiplexer.

Table 248. Interconnect to the ocref_clr input multiplexer

signal
comp1_out
comp2_out
comp3_out
comp4_out
comp5_out
comp6_out
comp7_out
Advanced-control timers (TIM1/TIM8/TIM20)
TIM8
comp2_out
comp3_out
comp4_out
comp5_out
comp6_out
comp7_out
Timer OCREF clear signals assignment
TIM1
comp1_out
comp2_out
comp3_out
comp4_out
comp5_out
comp6_out
comp7_out
Reserved
RM0440 Rev 1
TIM20
comp2_out
comp3_out
comp4_out
comp5_out
comp6_out
comp7_out
Enable bit in SYSCFG_CFGR2
register
CLL
PVDL
SPL
ECCL
None (always enabled)
TIM8
comp1_out
comp2_out
comp3_out
comp4_out
comp5_out
comp6_out
comp7_out
TIM20
1047/2083
1181