ST STM32G4 Series Reference Manual page 417

RM0440
Bits 31:10 Reserved, must be kept at reset value.
14.5.12 Pending register 2 (EXTI_PR2)
Address offset: 0x34
Reset value: undefined
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:10 Reserved, must be kept at reset value.
Bits 9:8 SWIx: Software interrupt on line x (x = 40 to 41)
If the interrupt is enabled on this line in EXTI_IMR, writing a '1' to this bit when it
is at '0' sets the corresponding pending bit of EXTI_PR resulting in an interrupt
request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a '1'
to the bit).
Bits 7:2 Reserved, must be kept at reset value.
Bits 1:0 SWIx: Software interrupt on line x (x = 32 to 33)
If the interrupt is enabled on this line in EXTI_IMR, writing a '1' to this bit when it
is at '0' sets the corresponding pending bit of EXTI_PR resulting in an interrupt
request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a '1'
to the bit).
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. PIF41
rc_w1
Bits 9:8 PIFx: Pending interrupt flag on line x (x = 40 to 41)
0: No trigger request occurred
1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the interrupt line. This bit
is cleared by writing a '1' into the bit.
Bits 7:2 Reserved, must be kept at reset value.
Bits 1:0 PIFx: Pending interrupt flag on line x (x = 32 to 33)
0: No trigger request occurred
1: Selected trigger request occurred
This bit is set when the selected edge event arrives on the interrupt line. This bit
is cleared by writing a '1' into the bit.
Extended interrupts and events controller (EXTI)
24 23 22
Res. Res. Res. Res.
8 7 6
PIF40 Res. Res. Res.
rc_w1
RM0440 Rev 1
21 20 19 18
Res. Res. Res.
5 4 3 2
Res. Res. Res.
17 16
Res. Res.
1 0
PIF33 PIF32
rc_w1 rc_w1
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