ST STM32G4 Series Reference Manual page 672

Analog-to-digital converters (ADC)
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 JDATA[15:0]: Injected data
20.6.19 ADC Analog Watchdog 2 Configuration Register (ADC_AWD2CR)
Address offset: 0xA0
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:19 Reserved, must be kept at reset value.
Bits 18:0 AWD2CH[18:0]: Analog watchdog 2 channel selection
These bits are set and cleared by software. They enable and select the input channels to be guarded
by the analog watchdog 2.
AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2
AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2
When AWD2CH[18:0] = 000..0, the analog Watchdog 2 is disabled
Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers.
The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
20.6.20 ADC Analog Watchdog 3 Configuration Register (ADC_AWD3CR)
Address offset: 0xA4
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
672/3748
These bits are read-only. They contain the conversion result from injected channel y. The
data are left -or right-aligned as described in
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
Section 20.4.26: Data
24 23 22 21
Res. Res. Res. Res.
8 7 6
AWD2CH[15:0]
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
AWD3CH[15:0]
rw rw rw
RM0440 Rev 1
management.
20 19 18
Res. Res. AWD2CH[18:16]
rw
5 4 3 2
rw rw rw
21 20 19 18
Res. Res. Res.
5 4 3 2
rw rw rw rw
RM0440
17 16
rw rw
1 0
rw rw
17 16
AWD3CH[18:16]
1 0
rw rw