Forcing Boot From Flash Memory; Flash Interrupts; Table 16. Flash Interrupt Request; Figure 5. Example Of Disabling Core Debug Access - ST STM32G4 Series Reference Manual

Embedded Flash memory (FLASH) for category 3 devices
In RDP level 2, the debugger is disabled by hardware, but in other RDP levels, the debugger
can be disabled by software using the bit DBG_SWEN in the FLASH_ACR register.
Figure 8
Power up
3.5.6

Forcing boot from Flash memory

To increase the security and establish a chain of trust, the BOOT_LOCK option bit of the
FLASH_SEC1R/FLASH_SEC2R register allows forcing the system to boot from the Main
Flash memory regardless the other boot options. It is always possible to set the
BOOT_LOCK bit. However, it is possible to reset it only when:
•
RDP is set to Level 0, or
•
RDP is set to Level 1, while Level 0 is requested and a full mass-erase is performed.
3.6

FLASH interrupts

Interrupt event
End of operation
Operation error
Read error
ECC correction
1. EOP is set only if EOPIE is set.
2. OPERR is set only if ERRIE is set.
124/2083
gives an example of managing DBG_SWEN and SEC_PROT bits.

Figure 5. Example of disabling core debug access

Securable memory not secured
Debug
enabled
Option
Execution of code
byte
within securable memory
loading
DBG_SWEN = 0

Table 16. Flash interrupt request

Event flag
(1)
EOP
(2)
OPERR
RDERR
ECCC
SEC_PROT = 0
Debug
disabled
DBG_SWEN = 1 SEC_PROT = 1
Software management
Event flag/interrupt
clearing method
Write EOP=1
Write OPERR=1
Write RDERR=1
Write ECCC=1
RM0440 Rev 1
SEC_PROT = 1
Securable memory secured
Debug
enabled
Execution of code
outside securable memory
Interrupt enable control
RDERRIE
ECCCIE
RM0440
timeline
MSv42192V1
bit
EOPIE
ERRIE