Table 319. Aes Interrupt Requests; Table 320. Processing Latency (In Clock Cycle) For Ecb, Cbc And Ctr; Figure 526. Aes Interrupt Signal Generation - ST STM32G4 Series Reference Manual

RM0440
Flags
Bits of AES_CR register
Each AES interrupt source can individually be enabled/disabled, by setting/clearing the
corresponding enable bit of the AES_CR register. See
The status of the individual maskable interrupt sources is read from the AES_SR register.
Table 319
33.6 AES processing latency
The tables below summarize the latency to process a 128-bit block for each mode of
operation.

Table 320. Processing latency (in clock cycle) for ECB, CBC and CTR

Key size Mode of operation
Mode 1: Encryption
Mode 2: Key derivation
128-bit
Mode 3: Decryption
Mode 4: Key derivation then
decryption
Mode 1: Encryption
Mode 2: Key derivation
256-bit
Mode 3: Decryption
Mode 4: Key derivation then
decryption

Figure 526. AES interrupt signal generation

CCF
CCFIE
WRERR
in AES_SR register
ERRIE
RDERR
ERRIE
gives a summary of the interrupt sources, their event flags and enable bits.

Table 319. AES interrupt requests

AES interrupt event
computation completed flag
read error flag
write error flag
Input
Algorithm phase +
FSM set
ECB, CBC, CTR 9
- -
ECB, CBC, CTR 9
ECB, CBC 9
ECB, CBC, CTR 13
- -
ECB, CBC, CTR 13
ECB, CBC 13
RM0440 Rev 1
AES hardware accelerator (AES)
aes_it
(goes to NVIC)
Figure 526.
Event flag
CCF
RDERR
WRERR
Computation Output
phase phase
38
59
38
93
58
82
58
128
MSv42162V1
Enable bit
CCFIE
ERRIE
ERRIE
Total
4 51
- 59
4 51
4 106
4 75
- 82
4 75
4 145
1483/2083
1497