Table 239. Interconnect To The Tim_Ti1 Input Multiplexer - ST STM32G4 Series Reference Manual

Advanced-control timers (TIM1/TIM8/TIM20)
Internal signal name
tim_ocref_clr[7:0]
tim_brk_cmp[7:1]
tim_brk2_cmp[7:1]
tim_sys_brk[n:0]
tim_pclk
tim_ker_ck
tim_cc_it
tim_upd_it
tim_brk_terr_ierr_it
tim_trg_com_dir_idx_it
tim_cc1_dma
tim_cc2_dma
tim_cc3_dma
tim_cc4_dma
tim_upd_dma
tim_trg_dma
tim_com_dma
Table 239,
input multiplexers.
tim_ti1 inputs
tim_ti1_in0
tim_ti1_in1
tim_ti1_in2
tim_ti1_in3
tim_ti1_in4
tim_ti1_in[5..15]
1044/2083
Table 238. TIM internal input/output signals (continued)
Signal type
Table 240, Table 241

Table 239. Interconnect to the tim_ti1 input multiplexer

TIM1
TIM1_CH1
comp1_out
comp2_out
comp3_out
comp4_out
Timer tim_ocref_clr input bus. These inputs
can be used to clear the tim ocxref signals,
Input
typically for hardware cycle-by-cycle
pulsewidth control.
Input Break input for internal signals
Input Break2 input for internal signals
System break input. This input gathers the
Input
MCU's system level errors.
Input Timer APB clock
Timer kernel clock. This clock must be
synchronous with tim_pclk (derived from the
Input same source). The clock ratio
tim_ker_ck/tim_pclk must be an integer:1, 2,
3,..., 16 (maximum value)
Output Timer capture/compare interrupt
Output Timer update event interrupt
Timer break, break2, transition error and
Output
index error interrupt
Timer trigger, commutation, direction and
Output
index interrupt
Output Timer capture / compare 1..4 dma requests
Output Timer update dma request
Output Timer trigger dma request
Output Timer commutation dma request
and Table 242 list the sources connected to the tim_ti[1..4]
Sources
TIM8_CH1
comp1_out
comp2_out
comp3_out
comp4_out
Reserved
RM0440 Rev 1
Description
TIM8
TIM20_CH1
comp1_out
comp2_out
comp3_out
comp4_out
RM0440
TIM20