Figure 358. Counter Timing Diagram, Internal Clock Divided By 1; Figure 359. Counter Timing Diagram, Internal Clock Divided By 2 - ST STM32G4 Series Reference Manual

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
1192/2083

Figure 358. Counter timing diagram, internal clock divided by 1

tim_psc_ck
CEN
tim_cnt_ck
31
(UIF)

Figure 359. Counter timing diagram, internal clock divided by 2

tim_psc_ck
CEN
tim_cnt_ck
0034
(UIF)
32 34 35 36 00
33
0035 0036
RM0440 Rev 1
01 02
03 04 05
0000 0001 0002
RM0440
06 07
MSv50997V1
0003
MSv62300V1