Figure 302. Data Format And Register Coding In Dithering Mode - ST STM32G4 Series Reference Manual

RM0440
2. The ARR[3:0] bits must be reset
3. The DITHEN bit must be reset
4. The CCIF flags must be cleared
5. The CEN bit can be set ( eventually with ARPE = 1).

Figure 302. Data format and register coding in dithering mode

Register format in
dithering mode
Example
The minimum frequency is given by the following formula:
Note: The maximum TIMx_ARR and TIMxCCRy values are limited to 0xFFFEF in dithering mode
(corresponds to 65534 for the integer part and 15 for the dithered part).
As shown on the
resolution whatever the PWM frequency.
b19
MSB: 16-bits, integer part
b19
Base compare value is 20 during 16 periods
Resolution
Dithering mode disabled: F
Dithering mode enabled: F
Figure 303 below, the dithering mode allows to increase the PWM
Advanced-control timers (TIM1/TIM8/TIM20)
326
20
F
Tim
------------- -
⇒ F
= =
pwmMin
F
pwm
pwmMin
pwmMin
RM0440 Rev 1
LSB: 4-bits
fractional part
6
Additional 6 cycles are spread over the
16 periods
F
Tim
------------------------------------ -
Max
Resolution
F
Tim
--------------- -
=
65536
F
Tim
----------------------------- -
=
15
----- -
65535 +
16
b0
b0
MSv45753V2
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