ST STM32G4 Series Reference Manual page 399

RM0440
13 Nested vectored interrupt controller (NVIC)
13.1 NVIC main features
•
102 maskable interrupt channels (not including the sixteen Cortex
interrupt lines)
•
16 programmable priority levels (4 bits of interrupt priority are used)
•
Low-latency exception and interrupt handling
•
Power management control
• Implementation of System Control Registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to the PM0214 programming manual for
Cortex TM
13.2 SysTick calibration value register
The SysTick calibration value is set to 0x3E8, which gives a reference time base of 1 ms
with the SysTick clock set to 125 KHz (1 MHz / 8).
-M4 products.
Nested vectored interrupt controller (NVIC)
RM0440 Rev 1
®
-M4 with FPU
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