Error Code Correction (Ecc); Read Access Latency; Table 19. Number Of Wait States According To Cpu Clock (Hclk) Frequency - ST STM32G4 Series Reference Manual

RM0440
4.3.2

Error code correction (ECC)

Data in Flash memory are 72-bits words: 8 bits are added per double word (64 bits). The
ECC mechanism supports:
•
One error detection and correction
•
Two errors detection
When one error is detected and corrected, the flag ECCC (ECC correction) is set in
ECC register
When two errors are detected, a flag ECCD (ECC detection) is set in FLASH_ECCR
register. In this case, a NMI is generated.
When an ECC error is detected, the address of the failing double word is saved in
ADDR_ECC[20:0] in the FLASH_ECCR register. ADDR_ECC[2:0] are always cleared.
When ECCC or ECCD is set, ADDR_ECC is not updated if a new ECC error occurs.
FLASH_ECCR is updated only when ECC flags are cleared.
Note: For a virgin data: 0xFF FFFF FFFF FFFF FFFF, one error is detected and corrected but two
errors detection is not supported.
When an ECC error is reported, a new read at the failing address may not generate an ECC
error if the data is still present in the current buffer, even if ECCC and ECCD are cleared.
4.3.3

Read access latency

To correctly read data from Flash memory, the number of wait states (LATENCY) must be
correctly programmed in the
frequency of the CPU clock (HCLK) and the internal voltage range of the device V
Refer to
correspondence between wait states and CPU clock frequency.

Table 19. Number of wait states according to CPU clock (HCLK) frequency

Wait states (WS)
0 WS (1 CPU cycles)
1 WS (2 CPU cycles)
2 WS (3 CPU cycles)
3 WS (4 CPU cycles)
4 WS (5 CPU cycles)
5 WS (6 CPU cycles)
6 WS (7 CPU cycles)
7 WS (7 CPU cycles)
8 WS (7 CPU cycles)
After reset, the CPU clock frequency is 16 MHz and 1 wait state (WS) is configured in the
FLASH_ACR register.
Embedded Flash memory (FLASH) for category 2 devices
(FLASH_ECCR). If ECCCIE is set, an interrupt is generated.
Flash access control register (FLASH_ACR)
Section 5.1.9: Dynamic voltage scaling
(LATENCY)
management.
V Range 1
CORE
≤ 20
≤ 40
≤ 60
≤ 80
≤ 100
≤ 120
≤ 140
≤ 160
≤ 170
RM0440 Rev 1
according to the
Table 19 shows the
HCLK (MHz)
V Range 2
CORE
≤ 8
≤ 16
≤ 26
-
-
-
-
-
-
Flash
.
CORE
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