ST STM32G4 Series Reference Manual page 721

RM0440
21.7.10 Dual DAC 12-bit left aligned data holding register
(DAC_DHR12LD)
Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:20 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data
Bits 19:16 Reserved, must be kept at reset value.
Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
Bits 3:0 Reserved, must be kept at reset value.
21.7.11 Dual DAC 8-bit right aligned data holding register
(DAC_DHR8RD)
Address offset: 0x28
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
DACC2DHR[7:0]
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel2.
Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel1.
28 27 26 25
DACC2DHR[11:0]
rw rw rw rw
12 11 10 9
DACC1DHR[11:0]
rw rw rw rw
These bits are written by software which specifies 12-bit data for DAC channel2.
These bits are written by software which specifies 12-bit data for DAC channel1.
27 26 25
Res. Res. Res.
11 10 9
rw rw rw rw
24 23 22
rw rw rw
8 7 6
rw rw rw
24 23 22
Res. Res. Res. Res.
8 7 6
rw rw rw
RM0440 Rev 1
Digital-to-analog converter (DAC)
21 20 19 18
Res. Res.
rw rw
5 4 3 2
Res. Res.
rw rw
21 20 19 18
Res. Res. Res.
5 4 3 2
DACC1DHR[7:0]
rw rw rw rw
17 16
Res. Res.
1 0
Res. Res.
17 16
Res. Res.
1 0
rw rw
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