Figure 153. Dual-Channel Dac Block Diagram - ST STM32G4 Series Reference Manual

Digital-to-analog converter (DAC)
21.4 DAC functional description
21.4.1 DAC block diagram
dac_ch1_trg0
dac_ch1_trg15
dac_ch1_dma
dac_unr_it
dac_hclk
dac_ch2_dma
dac_ch2_trg0
dac_ch2_trg15
1. MODEx bits in the DAC_MCR control the output mode and allow switching between the Normal mode in
buffer/unbuffered configuration and the Sample and Hold mode.
2. Refer to
3. DAC channel2 is available only on DAC1, DAC3 and DAC4.
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Figure 153. Dual-channel DAC block diagram

TRIG
TSEL1
[3:0]
bits
Control registers
& logic Channel1
DAC channel 1
Control registers
& logic Channel2
TSEL2
[3:0]
bits
TRIG
DAC channel 2
Section 21.3: DAC implementation
Offset
calibration
OTRIM1[5:0]
bits
MODE1 bits
DOR1
converter 1
12-bit
Sample & Hold
TSAMPLE1
THOLD1
lsi_ck/
lse_ck
TREFRESH1
Offset
calibration
OTRIM2[5:0]
bits
MODE2 bits
DOR2
converter 2
12-bit
Sample & Hold
registers
TSAMPLE2
lsi_ck/ THOLD2
lse_ck
TREFRESH2
for channel2 availability.
RM0440 Rev 1
VDDA
Buffer
DAC 1
registers
Buffer
DAC
2
VSSA
RM0440
dac_out1
dac_out2
MSv46134V3