ST STM32G4 Series Reference Manual page 30

Contents
29.4.26 Timer synchronization (TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1343
29.4.27 TIM15/TIM16/TIM17 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . 1343
29.4.28 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1343
29.5 TIM15/TIM16/TIM17 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . 1343
29.6 TIM15/TIM16/TIM17 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344
29.7 TIM15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1345
29.7.1
29.7.2
29.7.3
29.7.4
29.7.5
29.7.6
29.7.7
29.7.8
29.7.9
29.7.10 TIM15 counter (TIM15_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1360
29.7.11 TIM15 prescaler (TIM15_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1360
29.7.12 TIM15 auto-reload register (TIM15_ARR) . . . . . . . . . . . . . . . . . . . . . 1361
29.7.13 TIM15 repetition counter register (TIM15_RCR) . . . . . . . . . . . . . . . . 1361
29.7.14 TIM15 capture/compare register 1 (TIM15_CCR1) . . . . . . . . . . . . . . 1362
29.7.15 TIM15 capture/compare register 2 (TIM15_CCR2) . . . . . . . . . . . . . . 1363
29.7.16 TIM15 break and dead-time register (TIM15_BDTR) . . . . . . . . . . . . 1363
29.7.17 TIM15 timer deadtime register 2 (TIM15_DTR2) . . . . . . . . . . . . . . . . 1366
29.7.18 TIM15 input selection register (TIM15_TISEL) . . . . . . . . . . . . . . . . . 1367
29.7.19 TIM15 alternate function register 1 (TIM15_AF1) . . . . . . . . . . . . . . . 1368
29.7.20 TIM15 alternate function register 2 (TIM15_AF2) . . . . . . . . . . . . . . . 1370
29.7.21 TIM15 DMA control register (TIM15_DCR) . . . . . . . . . . . . . . . . . . . . 1371
29.7.22 TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . . . . . . . . 1371
29.7.23 TIM15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1372
29.8 TIM16/TIM17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375
29.8.1
29.8.2
29.8.3
29.8.4
29.8.5
30/2083
TIM15 control register 1 (TIM15_CR1) . . . . . . . . . . . . . . . . . . . . . . . 1345
TIM15 control register 2 (TIM15_CR2) . . . . . . . . . . . . . . . . . . . . . . . 1346
TIM15 slave mode control register (TIM15_SMCR) . . . . . . . . . . . . . 1348
TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . . . . . . . . . 1349
TIM15 status register (TIM15_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1350
TIM15 event generation register (TIM15_EGR) . . . . . . . . . . . . . . . . 1352
TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353
TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355
TIM15 capture/compare enable register (TIM15_CCER) . . . . . . . . . 1357
TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . . . . . . . . . . . . 1375
TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . . . . . . . . . . . . 1376
TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . 1377
TIMx status register (TIMx_SR)(x = 16 to 17) . . . . . . . . . . . . . . . . . . 1378
TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . . . . . 1379
RM0440 Rev 1
RM0440