Digital-to-analog converter (DAC)
Table 185. DAC register map and reset values (continued)
Register
Offset
name
DAC_SR
0x34
Reset value
0
0
DAC_CCR
0x38
Reset value
DAC_MCR
0x3C
Reset value
DAC_
SHSR1
0x40
Reset value
DAC_
SHSR2
0x44
Reset value
DAC_
SHHR
0x48
Reset value
DAC_
SHRR
0x4C
Reset value
DAC_
STR1
0x58
Reset value
0
0
DAC_STR2
0x5C
Reset value
0
0
DAC_
STMODR
0x60
Reset value
Refer to
732/2083
0
0
0
0
0
THOLD2[9:0]
0
0
0
0
0
0
STINCDATA1[15:0]
0
0
0
0
0
0
0
0
STINCDATA2[15:0]
0
0
0
0
0
0
0
0
STINCTRIG
SEL2[3:0]
0
0
0
0
Section 2.2 on page 78
0
0
OTRIM2[4:0]
X
X X X X
MODE2
[2:0]
0
0
0
0
0
0
0
0
0
0
1
TREFRESH2[7:0]
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
STRSTTRIG
SEL2[3:0]
0
0
0
0
for the register boundary addresses.
RM0440 Rev 1
0
0
0
0
0
TSAMPLE1[9:0]
0
0
0
0
TSAMPLE2[9:0]
0
0
0
0
THOLD1[9:0]
0
0
0
0
TREFRESH1[7:0]
0
0
STRSTDATA1[11:0]
0
0
0
0
0
0
STRSTDATA2[11:0]
0
0
0
0
0
0
STINCTRIG
SEL1[3:0]
0
0
0
0
RM0440
OTRIM1[4:0]
X
X
X
X
X
MODE1
[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
STRSTTRIG
SEL1[3:0]
0
0
0
0
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