Figure 343. Index Behavior In Clock + Direction Mode, Ipos[0] = 1; Figure 344. Index Behavior In Directional Clock Mode, Ipos[0] = 1 - ST STM32G4 Series Reference Manual

Advanced-control timers (TIM1/TIM8/TIM20)
Index management in non-quadrature mode
The Figure 343
mode and clock plus direction mode, when the SMS[3:0] bitfield is equal to 1010, 1011,
1100, 1101.
For both of these modes, the index sensitivity is set with the IPOS[0] bit as following:
•
IPOS[0] = 0: Index is detected on clock low level
•
IPOS[0] = 1: Index is detected on clock high level
The IPOS[1] bit is not-significant.
Counter x2 mode
Counter x1 mode
Counter x2 mode
Counter x1 mode
Encoder error management
For encoder configurations where 2 quadrature signals are available, it is possible to detect
transition errors. The reading on the 2 inputs corresponds to a 2-bit gray code which can be
represented as a state diagram, on the
at once. An erroneous transition will set the TERRF interrupt flag in the TIMx_SR status
1116/2083
and Figure 344 below detail how the index is managed in directional clock

Figure 343. Index behavior in clock + direction mode, IPOS[0] = 1

tim_ti1
tim_ti2
Index
7 0
7 0

Figure 344. Index behavior in directional clock mode, IPOS[0] = 1

tim_ti1
tim_ti2
DIR bit
9 0
9
0
1 2 3
1
1 2 3
1
Figure 345. below. A single bit is expected to change
RM0440 Rev 1
4 3 2 7 6
2 1
4 3 2 1 0
2 1
RM0440
5
7
MSv62355V1
9 8
0
9
MSv62356V1