Table 232. Hrtim Interrupt Summary - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus
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RM0440
14 interrupts can be generated by each timing unit:
Delayed protection triggered
Counter reset or roll-over event
Output 1 and output 2 reset (transition active to inactive)
Output 1 and output 2 set (transition inactive to active)
Capture 1 and 2 events
Timing unit registers update
Repetition event
Compare 1 to 4 event
8 global interrupts are generated for the whole HRTIM:
System fault and fault 1 to 6 (regardless of the timing unit attribution)
DLL calibration done
Burst mode period completed
The interrupt requests are grouped in 8 vectors as follows:
hrtim_it1: master timer interrupts (master update, sync Input, repetition, MCMP1..4)
and global interrupt except faults (burst mode period and DLL ready interrupts)
hrtim_it2: TIMA interrupts
hrtim_it3: TIMB interrupts
hrtim_it4: TIMC interrupts
hrtim_it5: TIMD interrupts
hrtim_it6: TIME interrupts
hrtim_it7: TIMF interrupts
hrtim_it8: Dedicated vector all fault interrupts to allow high-priority interrupt handling
Table 232
status bits.
Interrupt
vector
hrtim_it1
is a summary of the interrupt requests, their mapping and associated control, and

Table 232. HRTIM interrupt summary

Interrupt event
Burst mode period completed
DLL calibration done
Master timer registers update
Synchronization event received
Master timer repetition event
Master compare 1 to 4 event
Event flag
BMPER
DLLRDY
MUPD
SYNC
MREP
MCMP1
MCMP2
MCMP3
MCMP4
RM0440 Rev 1
High-resolution timer (HRTIM)
Enable
Flag clearing
control bit
BMPERIE
BMPERC
DLLRDYIE
DLLRDYC
MUPDIE
MUPDC
SYNCIE
SYNCC
MREPIE
MREPC
MCMP1IE
MCP1C
MCMP2IE
MCP2C
MCMP3IE
MCP3C
MCMP4IE
MCP4C
bit
903/2083
1040

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