Figure 416. Index Behavior In X1 And X2 Mode (Ipos[1:0] = 01) - ST STM32G4 Series Reference Manual

RM0440
AB = IPOS[1:0] = 01
Directional index sensitivity
The IDIR[1:0] bitfield in the TIMx_ECR register allows the index to be active only in a
selected counting direction.
The Figure 417
depending on IDIR[1:0] value.
Note: The IDR[1:0] bitfield must be written when IE bit is reset (index mode disabled).
Note: The directional index sensitivity is not supported in clock + direction mode. When
SMS[3:0] = 1010 or 1011, the IDIR[1:0] must be set to 00.

Figure 416. Index behavior in x1 and x2 mode (IPOS[1:0] = 01)

Channel A
Channel B
Index
DIR bit
Counter x2 10 11
Counter x1 5
below shows the relationship between index and counter reset events,
RM0440 Rev 1
General-purpose timers (TIM2/TIM3/TIM4/TIM5)
0 1 2 1
6 7
0 11 10 9
0 1 3
8
MSv45773V1
1241/2083
1297