Table 350. Lpuart Register Map And Reset Values - ST STM32G4 Series Reference Manual

RM0440
37.5.13 LPUART register map
The table below gives the LPUART register map and reset values.
Register
Offset
name
LPUART_
CR1
FIFO mode
0x00
enabled
Reset value 0 0 0 0
LPUART_
CR1
FIFO mode
0x00
disabled
Reset value
LPUART_
CR2
0x04
Reset value 0 0 0 0 0 0 0 0
LPUART_
CR3
0x08
Reset value 0 0 0 0 0 0 0
LPUART_
BRR
0x0C
Reset value
0x10-
0x14
LPUART_
RQR
0x18
Reset value
LPUART_
ISR
FIFO mode
0x1C
enabled
Reset value
LPUART_
ISR
FIFO mode
0x1C
disabled
Reset value
Low-power universal asynchronous receiver transmitter (LPUART)

Table 350. LPUART register map and reset values

DEAT[4:0]
0 0 0 0 0 0 0 0 0 0
DEAT[4:0]
0 0 0 0 0 0 0 0 0 0 0 0
ADD[7:0]
0 0 0 0
0 0 0 1 0 0 0 0 0 0 0
0 0 0 0 0 0 0
RM0440 Rev 1
DEDT[4:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DEDT[4:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
STO
P[1:
0 0 0 0 0 0 0
WU
S
[1:0
]
0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
0]
0 0 0 0 0
BRR[19:0]
0 0 1 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0
0
0 0
0 0 0 0
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