ST STM32G4 Series Reference Manual page 959

RM0440
Bit 5 Reserved, must be kept at reset value.
Bits 4:1 EE6FLTR[3:0]: External event 6 filter
Refer to EE1FLTR[3:0] description.
Bit 0 EE6LTCH: External event 6 latch
Refer to EE1LTCH description.
26.5.33 HRTIM timer A reset register (HRTIM_RSTAR)
Address offset: 0x0D4
Reset value: 0x0000 0000
31 30 29
TIMF TIME TIME TIME
CMP2 CMP4 CMP2 CMP1
rw rw rw
15 14 13
EXT EXT EXT EXT
EVNT7 EVNT6 EVNT5 EVNT4
rw rw rw
Bit 31 TIMFCPM2: Timer F compare 2
The timer A counter is reset upon timer F Compare 2 event.
Bit 30 TIMECPM4: Timer E compare 4
The timer A counter is reset upon timer E compare 4 event.
Bit 29 TIMECMP2: Timer E compare 2
The timer A counter is reset upon timer E compare 2 event.
Bit 28 TIMECMP1: Timer E compare 1
The timer A counter is reset upon timer E compare 1 event.
Bit 27 TIMDCMP4: Timer D compare 4
The timer A counter is reset upon timer D compare 4 event.
Bit 26 TIMDCMP2: Timer D compare 2
The timer A counter is reset upon timer D compare 2 event.
Bit 25 TIMDCMP1: Timer D compare 1
The timer A counter is reset upon timer D compare 1 event.
Bit 24 TIMCCMP4: Timer C compare 4
The timer A counter is reset upon timer C compare 4 event.
Bit 23 TIMCCMP2: Timer C compare 2
The timer A counter is reset upon timer C compare 2 event.
Bit 22 TIMCCMP1: Timer C compare 1
The timer A counter is reset upon timer C compare 1 event.
Bit 21 TIMBCMP4: Timer B compare 4
The timer A counter is reset upon timer B compare 4 event.
Bit 20 TIMBCMP2: Timer B compare 2
The timer A counter is reset upon timer B compare 2 event.
28 27 26 25
TIMD TIMD TIMD
CMP4 CMP2 CMP1
rw rw rw rw
12 11 10 9
EXT EXT EXT
EVNT3 EVNT2 EVNT1
rw rw rw rw
24 23 22
TIMC TIMC TIMC TIMB
CMP4 CMP2 CMP1 CMP4
rw rw rw
8 7 6
MST MST MST
CMP4 CMP3 CMP2 CMP1
rw rw rw
RM0440 Rev 1
High-resolution timer (HRTIM)
21 20 19 18
EXT
TIMB TIMB
EVNT
CMP2 CMP1
10
rw rw rw rw
5 4 3 2
MST MST
CMP4 CMP2
PER
rw rw rw rw
17 16
EXT EXT
EVNT9 EVNT8
rw rw
1 0
TIMF
UPDT
CMP1
rw rw
959/2083
1040