Table 76. Programmable Data Width And Endian Behavior (When Pinc = Minc = 1) - ST STM32G4 Series Reference Manual

RM0440
11.4.6 DMA data width, alignment and endianness
When PSIZE[1:0] and MSIZE[1:0] are not equal, the DMA controller performs some data
alignments as described in

Table 76. Programmable data width and endian behavior (when PINC = MINC = 1)

Source
Destinat
port
ion port
Number
width
width
of data
(PSIZE
(MSIZE
items to
if
if
transfer
DIR = 1,
DIR = 1,
(NDT)
else
else
MSIZE)
PSIZE)
8 8 8
8 16 4
8 32 4
16 8 4
16 16 4
16 32 4
32 8 4
32 16 4
32 32 4
Table
Source content:
address / data
(DMA_CMARx if
DIR = 1, else
DMA_CPARx)
@0x0 / B0 1: read B0[7:0] @0x0 then write B0[7:0] @0x0
@0x1 / B1 2: read B1[7:0] @0x1 then write B1[7:0] @0x1
@0x2 / B2 3: read B2[7:0] @0x2 then write B2[7:0] @0x2
@0x3 / B3 4: read B3[7:0] @0x3 then write B3[7:0] @0x3
@0x0 / B0 1: read B0[7:0] @0x0 then write 00B0[15:0] @0x0
@0x1 / B1 2: read B1[7:0] @0x1 then write 00B1[15:0] @0x2
@0x2 / B2 3: read B2[7:0] @0x2 then write 00B2[15:0] @0x4
@0x3 / B3 4: read B3[7:0] @0x3 then write 00B3[15:0] @0x6
@0x0 / B0 1: read B0[7:0] @0x0 then write 000000B0[31:0] @0x0
@0x1 / B1 2: read B1[7:0] @0x1 then write 000000B1[31:0] @0x4
@0x2 / B2 3: read B2[7:0] @0x2 then write 000000B2[31:0] @0x8
@0x3 / B3 4: read B3[7:0] @0x3 then write 000000B3[31:0] @0xC
@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write B0[7:0] @0x0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write B2[7:0] @0x1
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write B4[7:0] @0x2
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write B6[7:0] @0x3
@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write B1B0[15:0] @0x0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write B3B2[15:0] @0x2
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write B5B4[15:0] @0x4
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write B7B6[15:0] @0x6
@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write 0000B1B0[31:0] @0x0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write 0000B3B2[31:0] @0x4
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write 0000B5B4[31:0] @0x8
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write 0000B7B6[31:0] @0xC
@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B0[7:0] @0x0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B4[7:0] @0x1
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write B8[7:0] @0x2
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BC[7:0] @0x3
@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B1B0[15:0] @0x0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B5B4[15:0] @0x2
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write B9B8[15:0] @0x4
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BDBC[15:0] @0x6
@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B3B2B1B0[31:0] @0x0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B7B6B5B4[31:0] @0x4
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write BBBAB9B8[31:0] @0x8
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BFBEBDBC[31:0] @0xC
RM0440 Rev 1
Direct memory access controller (DMA)
76.
DMA transfers
Destination
content:
address / data
(DMA_CPARx if
DIR = 1, else
DMA_CMARx)
@0x0 / B0
@0x1 / B1
@0x2 / B2
@0x3 / B3
@0x0 / 00B0
@0x2 / 00B1
@0x4 / 00B2
@0x6 / 00B3
@0x0 / 000000B0
@0x4 / 000000B1
@0x8 / 000000B2
@0xC / 000000B3
@0x0 / B0
@0x1 / B2
@0x2 / B4
@0x3 / B6
@0x0 / B1B0
@0x2 / B3B2
@0x4 / B5B4
@0x6 / B7B6
@0x0 / 0000B1B0
@0x4 / 0000B3B2
@0x8 / 0000B5B4
@0xC / 0000B7B6
@0x0 / B0
@0x1 / B4
@0x2 / B8
@0x3 / BC
@0x0 / B1B0
@0x2 / B5B4
@0x4 / B9B8
@0x6 / BDBC
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
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