Figure 272. Counter Timing Diagram, Internal Clock Divided By N; Figure 273. Counter Timing Diagram, Update Event When Arpe=0; (Timx_Arr Not Preloaded) - ST STM32G4 Series Reference Manual

Advanced-control timers (TIM1/TIM8/TIM20)
Counter overflow
Update event (UEV)
Update interrupt flag
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
1052/2083

Figure 272. Counter timing diagram, internal clock divided by N

tim_psc_ck
tim_cnt_ck
1F
Counter register
(UIF)

Figure 273. Counter timing diagram, update event when ARPE=0

tim_psc_ck
CEN
tim_cnt_ck
31
Counter register
Counter overflow
FF
Write a new value in TIMx_ARR
20

(TIMx_ARR not preloaded)

32 33 34 35 36
RM0440 Rev 1
00
00 01 03 04 05 06 07
02
36
RM0440
MSv62302V1
MSv62303V1