ST STM32G4 Series Reference Manual page 260

Reset and clock control (RCC)
6.4.10 AHB3 peripheral reset register (RCC_AHB3RSTR)
Address offset: 0x30
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 QSPIRST: QUADSPI reset
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 FMCRST: Flexible memory controller reset
6.4.11 APB1 peripheral reset register 1 (RCC_APB1RSTR1)
Address offset: 0x38
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
LPTIM1 I2C3 PWR
Res.
RST RST RST
rw rw
15 14 13
SPI3 SPI2
Res. Res.
RST RST
rw rw
260/2083
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
Set and cleared by software.
0: No effect
1: Reset QUADSPI
Set and cleared by software.
0: No effect
1: Reset FMC
28 27 26 25
FDCAN
Res. Res.
RST
rw rw
12 11 10 9
Res. Res. Res.
24 23 22
Res. Res. Res.
8 7 6
QSPIRST Res. Res.
rw
24 23 22 21
USB I2C2 I2C1
Res.
RST RST RST
rw rw rw
8 7 6
CRS TIM7
Res. Res.
RST RST
rw rw
RM0440 Rev 1
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. Res.
20 19 18
UART5 UART4 USART3
RST RST RST
rw rw rw
5 4 3 2
TIM6 TIM5 TIM4
RST RST RST
rw rw rw
RM0440
17 16
Res. Res.
1 0
FMC
Res.
RST
rw
17 16
USART2
Res.
RST
rw
1 0
TIM3 TIM2
RST RST
rw rw