ST STM32G4 Series Reference Manual page 64

List of figures RM0440
Figure 347. Down-counting encode error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119
Figure 348. Encoder mode change with preload transferred on update (SMSPS = 0) . . . . . . . . . . . 1120
Figure 349. Measuring time interval between edges on 3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
Figure 350. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123
Figure 351. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1124
Figure 352. Control circuit in Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
Figure 353. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126
Figure 354. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . 1127
Figure 355. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184
Figure 356. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1190
Figure 357. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1191
Figure 358. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192
Figure 359. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192
Figure 360. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193
Figure 361. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193
Figure 362. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . 1194
Figure 363. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . 1195
Figure 364. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196
Figure 365. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
Figure 366. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
Figure 367. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198
Figure 368. Counter timing diagram, Update event when repetition counter
is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198
Figure 369. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . 1200
Figure 370. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200
Figure 371. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . 1201
Figure 372. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
Figure 373. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . 1202
Figure 374. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . 1203
Figure 375. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1204
Figure 376. tim_ti2 external clock connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204
Figure 377. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205
Figure 378. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1206
Figure 379. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207
Figure 380. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 1207
Figure 381. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208
Figure 382. Output stage of capture/compare channel (channel 1, idem ch.2, 3 and 4) . . . . . . . . . . 1208
Figure 383. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211
Figure 384. Output compare mode, toggle on tim_oc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213
Figure 385. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214
Figure 386. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215
Figure 387. Dithering principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1216
Figure 388. Data format and register coding in dithering mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217
Figure 389. PWM resolution vs frequency (16-bit mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218
Figure 390. PWM resolution vs frequency (32-bit mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218
Figure 391. PWM dithering pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219
Figure 392. Dithering effect on duty cycle in center-aligned PWM mode . . . . . . . . . . . . . . . . . . . . . 1220
Figure 393. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . 1222
Figure 394. Combined PWM mode on channels 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223
Figure 395. OCREF_CLR input selection multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224
Figure 396. Clearing TIMx tim_ocxref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224
Figure 397. Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225
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