ST STM32G4 Series Reference Manual page 265

RM0440
Bit 11 TIM1RST: TIM1 timer reset
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGRST: SYSCFG + COMP + OPAMP + VREFBUF reset
6.4.14 AHB1 peripheral clock enable register (RCC_AHB1ENR)
Address offset: 0x48
Reset value: 0x0000 0100
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
Bits 31:13 Reserved, must be kept at reset value.
Bit 12 CRCEN: CRC clock enable
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 FLASHEN: Flash memory interface clock enable
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 FMACEN: FMAC enable
Bit 3 CORDICEN: CORDIC clock enable
Set and cleared by software.
0: No effect
1: Reset TIM1 timer
0: No effect
1: Reset SYSCFG + COMP + OPAMP + VREFBUF
28 27 26
Res. Res. Res. Res.
12 11 10
CRCEN Res. Res. Res.
rw
Set and cleared by software.
0: CRC clock disable
1: CRC clock enable
Set and cleared by software. This bit can be disabled only when the Flash is in power down
mode.
0: Flash memory interface clock disable
1: Flash memory interface clock enable
Set and reset by software.
0: FMAC clock disabled
1: FMAC clock enabled
Set and reset by software.
0: CORDIC clock disabled
1: CORDIC clock enabled
25 24 23 22
Res. Res. Res.
9 8 7 6
FLASH
Res. Res.
EN
rw
RM0440 Rev 1
Reset and clock control (RCC)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
FMAC CORDIC DMAM
Res.
EN EN UX1EN
rw rw rw
17 16
Res. Res.
1 0
DMA2 DMA1
EN EN
rw rw
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