Table 296. Tim Internal Input/Output Signals; Figure 475. Basic Timer Block Diagram - ST STM32G4 Series Reference Manual

RM0440
30.3 TIM6/TIM7 functional description
30.3.1 TIM6/TIM7 block diagram
tim_pck
tim_upd_it
tim_upd_dma
tim_psc_ck
Notes:
Reg
Preload registers transferred to active registers on U event according to control bit
Event
Interrupt & DMA
30.3.2 TIM6/TIM7 internal signals
The table in this section summarizes the TIM inputs and outputs.
Internal signal name
tim_pclk
tim_ker_ck
tim_trgo
tim_upd_it
tim_upd_dma

Figure 475. Basic timer block diagram

tim_ker_ck
IRQ interface
DMA interface
tim_cnt_ck
PSC
prescaler

Table 296. TIM internal input/output signals

Signal type
Input
Input
Output
Output
Output
Trigger controller
Control
Auto-reload register
Auto-reload register
UEV
Stop, clear or up
+ CNT counter
Timer APB clock
Timer kernel clock. This clock must be synchronous with
tim_pclk (derived from the same source). The clock ratio
tim_ker_ck/tim_pclk must be an integer:1, 2, 3,..., 16
(maximum value)
Internal trigger output. This trigger can trigger other on-
chip peripherals.
Timer update event interrupt
Timer update dma request
RM0440 Rev 1
Basic timers (TIM6/TIM7)
tim_trgo
Enable
Count
Update
Description
MSv62381V1
1401/2083
1417