ST STM32G4 Series Reference Manual page 254

Reset and clock control (RCC)
Bit 2 Reserved, must be kept at reset value.
Bit 1 LSERDYIE: LSE ready interrupt enable
Bit 0 LSIRDYIE: LSI ready interrupt enable
6.4.6 Clock interrupt flag register (RCC_CIFR)
Address offset: 0x1C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 HSI48RDYF: HSI48 ready interrupt flag
Bit 9 LSECSSF: LSE Clock security system interrupt flag
Bit 8 CSSF: Clock security system interrupt flag
Bits 7:6 Reserved, must be kept at reset value.
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Set and cleared by software to enable/disable interrupt caused by the LSE oscillator
stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Set and cleared by software to enable/disable interrupt caused by the LSI oscillator
stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
28 27 26 25
Res. Res. Res.
12 11 10 9
HSI48 LSE
Res.
RDYF CSSF
r r
Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a
response to setting the HSI48ON (refer to
Cleared by software setting the HSI48RDYC bit.
0: No clock ready interrupt caused by the HSI48 oscillator
1: Clock ready interrupt caused by the HSI48 oscillator
Set by hardware when a failure is detected in the LSE oscillator.
Cleared by software setting the LSECSSC bit.
0: No clock security interrupt caused by LSE clock failure
1: Clock security interrupt caused by LSE clock failure
Set by hardware when a failure is detected in the HSE oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
24 23 22
Res. Res. Res. Res.
8 7 6
CSSF Res. Res.
RDYF
r
Clock recovery RC register
RM0440 Rev 1
21 20 19 18
Res. Res. Res.
5 4 3 2
PLL HSE HSI
Res.
RDYF RDYF
r r r
(RCC_CRRCR)).
RM0440
17 16
Res. Res.
1 0
LSE LSI
RDYF RDYF
r r