RM0440
21.4.6
DAC output voltage
Digital inputs are converted to output voltages on a linear conversion between 0 and V
The analog output voltages on each DAC channel pin are determined by the following
equation:
DACoutput
21.4.7
DAC trigger selection
If the TENx control bit is set, conversion can then be triggered by an external event (timer
counter, external interrupt line). The TSELx[3:0] control bits determine which out of 16 pos-
sible events will trigger conversion as shown in bits TSEL1[3:0] and TSEL2[3:0] in .
Each time a DAC interface detects a rising edge on the selected trigger source (refer to the
table below), the last data stored into the DAC_DHRx register are transferred into the
DAC_DORx register. The DAC_DORx register is updated three dac_hclk cycles after the
trigger occurs.
If the software trigger is selected, the conversion starts once the SWTRIG bit is set.
SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the
DAC_DHRx register contents.
The reset trigger selection and the increment trigger selection of the sawtooth generation
are performed through STRSTTRIGSELx and STINCTRIGSELx control bits, respectively.
STRSTTRIGSELx mapping is similar to TSELx. Refer to
and
Table 179
Table 178
Note:
TSELx[3:0] bit cannot be changed when the ENx bit is set.
When software trigger is selected, the transfer from the DAC_DHRx register to the
DAC_DORx register takes only one dac_hclk clock cycle.
Table 173. DAC1 channel trigger and sawtooth reset trigger selection
DOR
------------- -
×
=
V
REF
4096
for TSELx and STRSTTRIGSELx mapping, and to
and
Table 180
for STINCTRIGSELx mapping.
Source
SWTRIG
TIM8_TRGO
TIM7_TRGO
TIM15_TRGO
TIM2_TRGO
TIM4_TRGO
EXTI9
TIM6_TRGO
Type
Software control bit
Internal signal from on-chip
timers
Internal signal from on-chip
timers
Internal signal from on-chip
timers
Internal signal from on-chip
timers
Internal signal from on-chip
timers
External pin
Internal signal from on-chip
timers
RM0440 Rev 1
Digital-to-analog converter (DAC)
Table
173,
Table
175,
Table
174,
Table
TSELx[3:0],
STRSTTRIGSELx[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
.
REF+
Table 177
176,
691/2083
732
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