ST STM32G4 Series Reference Manual page 286

Reset and clock control (RCC)
Bits 5:4 USART3SEL[1:0]: USART3 clock source selection
Bits 3:2 USART2SEL[1:0]: USART2 clock source selection
Bits 1:0 USART1SEL[1:0]: USART1 clock source selection
6.4.27 RTC domain control register (RCC_BDCR)
Address offset: 0x90
Reset value: 0x0000 0000
Reset by RTC domain Reset, except LSCOSEL, LSCOEN and BDRST which are reset only
by RTC domain power-on reset.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Note: The bits of the
As a result, after Reset, these bits are write-protected and the DBP bit in the
Power control register 1 (PWR_CR1)
Section 5.1.6: Battery backup domain on page 134
(except LSCOSEL, LSCOEN and BDRST) are only reset after a RTC domain Reset (see
Section 6.1.3: RTC domain
these bits.
31 30 29
Res. Res. Res. Res.
15 14 13
RTC
Res. Res. Res.
EN
rw
286/2083
This bit is set and cleared by software to select the USART3 clock source.
00: PCLK selected as USART3 clock
01: System clock (SYSCLK) selected as USART3 clock
10: HSI16 clock selected as USART3 clock
11: LSE clock selected as USART3 clock
This bit is set and cleared by software to select the USART2 clock source.
00: PCLK selected as USART2 clock
01: System clock (SYSCLK) selected as USART2 clock
10: HSI16 clock selected as USART2 clock
11: LSE clock selected as USART2 clock
This bit is set and cleared by software to select the USART1 clock source.
00: PCLK selected as USART1 clock
01: System clock (SYSCLK) selected as USART1 clock
10: HSI16 clock selected as USART1 clock
11: LSE clock selected as USART1 clock
RTC domain control register (RCC_BDCR)
reset). Any internal or external Reset will not have any effect on
28 27 26 25
LSCO
Res. Res.
SEL
rw
12 11 10 9
Res. Res. RTCSEL[1:0]
rw
has to be set before these can be modified. Refer to
for further information. These bits
24 23 22
LSCO
Res. Res. Res.
EN
rw
8 7 6
LSE LSE
Res.
CSSD CSSON
rw r
RM0440 Rev 1
are outside of the V
21 20 19 18
Res. Res. Res.
5 4 3 2
LSE
LSEDRV[1:0]
BYP
rw rw rw rw
RM0440
domain.
CORE
Section 5.4.1:
17 16
Res. BDRST
rw
1 0
LSE
LSEON
RDY
r rw