Figure 381. Capture/Compare Channel 1 Main Circuit; Figure 382. Output Stage Of Capture/Compare Channel (Channel 1, Idem Ch.2, 3 And 4) - ST STM32G4 Series Reference Manual

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
The output stage generates an intermediate waveform which is then used for reference:
tim_ocxref (active high). The polarity acts at the end of the chain.
Read CCR1H
S
read_in_progress
Read CCR1L
R
Input
CC1S[1]
mode
CC1S[0]
IC1PS
CC1E
CC1G
TIMx_EGR

Figure 382. Output stage of capture/compare channel (channel 1, idem ch.2, 3 and 4)

tim_ocref_clr
tim_etrf
tim_ocref_clr_int
CNT > CCR1
CNT = CCR1
tim_oc2ref
1. Available on some instances only. If not available, tim_etrf is directly connected to tim_ocref_clr_int.
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
1208/2083

Figure 381. Capture/compare channel 1 main circuit

MCU-peripheral interface
8
Capture/compare preload register
capture_transfer
Capture /compare shadow register
Capture
TIMx_SMCR
(1)
OCCS
0
1
tim_oc1ref
Output
mode
controller
OC1CE OC1M[3:0]
TIMx_CCMR2
APB Bus
8
write_in_progress
compare_transfer
Comparator
Counter
To the master
mode controller
tim_oc1refc
'0'
0
Output
1
selector
CC1E
TIMx_CCER
RM0440 Rev 1
write CCR1H
S
write CCR1L
R
Output
CC1S[1]
mode
CC1S[0]
OC1PE
UEV
(from time
base unit)
CNT>CCR1
CNT=CCR1
0
Output
enable
1
circuit
CC1P
CC1E TIMx_CCER
TIMx_CCER
MOE OSSI
OIS4 TIMx_CR2
RM0440
OC1PE
TIMx_CCMR1
MS31089V4
tim_oc1
TIMx_BDTR
MSv62374V1