ST STM32G4 Series Reference Manual page 904

High-resolution timer (HRTIM)
Interrupt
vector
hrtim_it2
hrtim_it3
hrtim_it4
hrtim_it5
hrtim_it6
hrtim_it7
hrtim_it8
26.3.23 DMA
Most of the events able to generate an interrupt can also generate a DMA request, even
both simultaneously. Each timer (master, TIMA...F) has its own DMA enable register.
The individual DMA requests are ORed into 7 channels as follows:
•
1 channel for the master timer
•
1 channel per timing unit (TIMA...F)
Note: Before disabling a DMA channel (DMA enable bit reset in TIMxDIER), it is necessary to
disable first the DMA controller.
Table 233
904/2083
Table 232. HRTIM interrupt summary (continued)
Interrupt event
Delayed protection triggered
Counter reset or roll-over event
Output 1 and output 2 reset (transition
active to inactive)
Output 1 and output 2 set (transition
inactive to active)
Capture 1 and 2 events
Timing unit registers update
Repetition event
Compare 1 to 4 event
System fault
Fault 1 to 6
is a summary of the events with their associated DMA enable bits.
Event flag
DLYPRT
RST
RSTx1
RSTx2
SETx1
SETx2
CPT1
CPT2
UPD
REP
CMP1
CMP2
CMP3
CMP4
SYSFLT
FLT1
FLT2
FLT3
FLT4
FLT5
FLT6
RM0440 Rev 1
RM0440
Enable Flag clearing
control bit bit
DLYPRTIE DLYPRTC
RSTIE RSTC
RSTx1IE RSTx1C
RSTx2IE RSTx2C
SETx1IE SETx1C
SETx2IE SETx2C
CPT1IE CPT1C
CPT2IE CPT2C
UPDIE UPDC
REPIE REPC
CMP1IE CMP1C
CMP2IE CMP2C
CMP3IE CMP3C
CMP4IE CMP4C
SYSFLTIE SYSFLTC
FLT1IE FLT1C
FLT2IE FLT2C
FLT3IE FLT3C
FLT4IE FLT4C
FLT5IE FLT5C
FLT6IE FLT6C