ST STM32G4 Series Reference Manual page 181

RM0440
4.7.10 Flash PCROP1 End address register (FLASH_PCROP1ER)
Address offset: 0x28
Reset value: 0xX000 XXXX. Register bits are loaded with values from Flash memory at
OBL.
Access: no wait state when no Flash memory operation is on going, word, half-word access.
PCROP_RDP bit can be accessed with byte access.
31 30 29
PCROP
Res. Res.
_RDP
rs
15 14 13
Res.
rw rw
Bits 30:15 Reserved, must be kept cleared
4.7.11 Flash WRP area A address register (FLASH_WRP1AR)
Address offset: 0x2C
Reset value: 0x00XX 00XX. Register bits are loaded with values from Flash memory at
OBL.
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
Bits 31:23 Reserved, must be kept cleared
Embedded Flash memory (FLASH) for category 2 devices
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
rw rw rw rw
Bit 31 PCROP_RDP: PCROP area preserved when RDP level decreased
This bit is set only. It is reset after a full mass erase due to a change of RDP
from Level 1 to Level 0.
0: PCROP area is not erased when the RDP level is decreased from Level 1 to
Level 0.
1: PCROP area is erased when the RDP level is decreased from Level 1 to
Level 0 (full mass erase).
Bits 14:0 PCROP1_END: PCROP area end offset
PCROP1_END contains the last double-word of the PCROP area.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
24 23 22
Res. Res. Res.
8 7 6
PCROP1_END[14:0]
rw rw rw
24 23 22
Res. Res.
rw
8 7 6
Res. Res.
rw
RM0440 Rev 1
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
21 20 19 18
WRP1A_END[6:0]
rw rw rw rw
5 4 3 2
WRP1A_STRT[6:0]
rw rw rw rw
17 16
Res. Res.
1 0
rw rw
17 16
rw rw
1 0
rw rw
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