ST STM32G4 Series Reference Manual page 899

RM0440
Dual channel DAC trigger
Slope compensation techniques and hysteretic control to be easily implemented using
HRTIM built-in features and the DAC sawtooth generator. The principle is to have a DAC
generating a decreasing saw-tooth synchronized with the PWM period, or a square wave
synchronized with PWM signal.
This mode is enabled with the DCDE bit in the TIMxCR2 register. This bit cannot be
changed once the timer is operating (TxEN bit set).
It uses two trigger outputs, as shown on the
- the hrtim_dac_reset_trgx generates DAC reset/update events
- the hrtim_dac_step_trgx generates requests for incremental DAC value changes
The DCDR bit in the TIMxCR2 register defines when the hrtim_dac_reset_trgx trigger is
generated:
•
DCDR = 0: the trigger is generated on counter reset or roll-over event
•
DCDR = 1: the trigger is generated on output 1 set event
Note: The DCDR bit is not significant when the DCDE bit is reset (Dual channel DAC trigger
disabled).
The DCDS bit in the TIMxCR2 register defines when the hrtim_dac_step_trgx trigger is
generated:
•
DCDS = 0: the trigger is generated on compare 2 event
•
DCDS = 1: the trigger is generated on output 1 reset event
The DCDR and DCDS bits allows the following use cases to be covered:
–
–
–
The compare 2 has a particular operating mode when the DCDE is set and the DCDS bit is
reset. The active comparison value is automatically updated as soon as a compare match
has occured, so that the trigger can be repeated periodically with a period equal to the
CMP2 value, as represented on
The dual channel DAC trigger with DCDS bit reset (compare 2 event used) must not be
used simultaneously with modes using CMP2 (triple / quad interleaved and triggered-half
modes).
Note: The CMP2 value can be changed on-the-fly. The new value is taken into account on the
next coming compare match.
Note: When the DCDS bit is reset, the CMP2 value must not be modified by other mechanisms:
the interleaved, triggered half and balanced idle modes must be disabled.
Edge-aligned slope compensation (DCDR = DCDS = 0): the DAC's sawtooth
starts on PWM period beginning and multiple triggers are generated during the
period
Center-aligned slope compensation (DCDR = 1 DCDS = 0): the DAC's sawtooth
starts on the output set event and multiple triggers are generated during the period
Hysteretic controller: the DAC value must be changed twice per period, when the
output state changes. 2 triggers are generated per PWM period. In edge-aligned
mode (DCDR=0, DCDS =1), the triggers are generated on counter reset or roll-
over. In center-aligned mode (DCDR=1, DCDS=1), the triggers are generated
when the output is set.
Figure 253
Figure 253.
RM0440 Rev 1
High-resolution timer (HRTIM)
below:
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