ST STM32G4 Series Reference Manual page 250

Reset and clock control (RCC)
Bits 3:2 SWS[1:0]: System clock switch status
Bits 1:0 SW[1:0]: System clock switch
6.4.4 PLL configuration register (RCC_PLLCFGR)
Address offset: 0x0C
Reset value: 0x0000 1000
Access: no wait state, word, half-word and byte access
This register is used to configure the PLL clock outputs according to the formulas:
• f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
• f(PLL_P) = f(VCO clock) / PLLP
• f(PLL_Q) = f(VCO clock) / PLLQ
• f(PLL_R) = f(VCO clock) / PLLR
31 30 29
PLLPDIV[4:0]
rw rw rw
15 14 13
Res.
rw rw
Bits 31:27 PLLPDIV[4:0]: Main PLLP division factor
250/2083
Set and cleared by hardware to indicate which clock source is used as system clock.
00: Reserved, must be kept at reset value
01: HSI16 oscillator used as system clock
10: HSE used as system clock
11: PLL used as system clock
Set and cleared by software to select system clock source (SYSCLK).
Configured by hardware to force HSI16 oscillator selection when exiting stop and standby
modes or in case of failure of the HSE oscillator.
00: Reserved, must be kept at reset value
01: HSI16 selected as system clock
10: HSE selected as system clock
11: PLL selected as system clock
28 27 26 25
PLLR[1:0]
rw rw rw rw
12 11 10 9
PLLN[6:0]
rw rw rw rw
Set and cleared by software to control the PLL "P" frequency. PLL "P" output clock frequency
= VCO frequency / PLLPDIV.
00000: PLL "P" clock is controlled by the bit PLLP
00001: Reserved.
00010: PLL "P" clock = VCO / 2
....
11111: PLL "P" clock = VCO / 31
24 23 22
PLL
Res. PLLQ[1:0]
REN
rw rw
8 7 6
PLLM[3:0]
rw rw rw
RM0440 Rev 1
21 20 19 18
PLL
Res. Res.
QEN
rw rw
5 4 3 2
Res. Res.
rw rw
RM0440
17 16
PLL
PLLP
PEN
rw rw
1 0
PLLSRC[1:0]
rw rw